Performance-Oriented Peephole Optimisation of Balsa Dual-Rail Circuits
نویسندگان
چکیده
The transparency and flexibility of the syntax-directed compilation technique, as used in the Tangram (now Haste) and Balsa synthesis systems, comes at the cost of performance overhead. Some control resynthesis and peephole optimisation techniques have been proposed to reduce this performance penalty. In this paper, we introduce new peephole optimisations for Balsa dual-rail circuits. The methods are oriented to remove redundant components and to increase the concurrency during return-to-zero phases. A novel control component, the ParSeq (a hybrid conditional parallel/sequencer controller) is also introduced. Simulations results using large, complex design examples, show substantial increases in performance with negligible area overhead.
منابع مشابه
UNIVERSITÄT AUGSBURG STG-Based Resynthesis for Balsa Circuits
Balsa provides a rapid development flow, where asynchronous circuits are created from high-level specifications, but the syntax-driven translation used by the Balsa compiler often results in performance overhead. To reduce this performance penalty, various control resynthesis and peephole optimization techniques are used; in this paper, STG-based resynthesis is considered. For this, we have tra...
متن کاملA Dual Rail Circuit Technique to Tolerate Routing Imbalances
Dual Rail Precharge (DRP) circuits, which are theoretically secure against differential power analysis attacks, suffer from an implementation problem: balancing routing capacitance of differential signals. To solve this, four proposals have been put forward: DWDDL [18], FatWire [19], Backend Duplication [4] and Three Phase Dual Rail [2]. Of these, three of them (DWDDL, FatWire, Backend Duplicat...
متن کاملSingle-Rail MOS Current Mode Logic Circuits for Low-Power and High- Speed Applications
Abstract MOS Current-Mode Logic (MCML) is usually used for high-speed applications. However, almost all MCML circuits are realized with dual-rail scheme. The dual-rail logic circuits increase extra area overhead and the complexity of the layout place and route. Moreover, little standard cells of the dualrail logic circuits have been developed for place-and-route tools, such as Cadence Encounter...
متن کاملLow Power Self-Timed Radix-2 Division
A self-timed radix-2 division scheme for low power consumption is proposed. By replacing dual-rail dynamic circuits in non-critical data paths with single-rail static circuits, power dissipation is decreased, yet performance is maintained by speculative remainder computation. SPICE simulation results show that the proposed design can achieve 33.8-ns latency for 56-bit mantissa division and 47% ...
متن کاملPattern Matching Strategies for Peephole Optimisation
Peephole optimisation is a simple and effective optimisation technique used in conventional compilers. In classical peephole optimisers, optimisation rules are commonly applied through string pattern matching by means of regular expressions. This string-based approach to matching has proven to be very effective, but it is just the syntax of the assembly code input that is processed and its mean...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2008